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Re: [OFF TOPIC] An embarrassing question
On Tue, 18 Feb 1997, Omer Zak wrote:
> > > We use 64Mb EDO on a P133 Motherboard motherboard with no problem at
> ^^^
>
> Since I seem to find no explanation what EDO means, could some kind soul
> please explain what does this mean and what is so special with EDO memory
> that it is worthy of mentioning when discussing computer specs?
>
> Until someone shows mercy on me and defines to me the term, I feel so out of
> fashion not knowing what does EDO mean.
a bit off topic, but here goes...
---------------------------------------------------
>From fink@POST.TAU.AC.IL Wed Feb 19 01:13:43 1997
Date: Sun, 9 Jun 1996 23:49:05 GMT
From: Udi Finkelstein <fink@POST.TAU.AC.IL>
To: Multiple recipients of list IL-BOARD <IL-BOARD@taunivm.tau.ac.il>
Subject: Re: All you need to know about EDO RAM.
On 9 Jun 1996 04:34:41 -0000, relkay01@FIU.EDU (Ron Elkayam) wrote:
>> EDO is not SUPPORTED on any chipset under a Pentium.
>> another fact of life: EDO SIMMS have NO parity bits. gotcha.
No EDO SIMMs on the market has a parity bit because there is no demand for it.
i.e., until the Triton II was out just recently, there were NO Pentium
chipsets which supports the parity bit and EDO mode. Since no chipsets exists,
no market demand for 9 bit EDO, hence no 9 bit EDO SIMMs. kapish?
>I said it uses the parity bit as a cache i.e. not for parity checking.
He He.. That was a good one!
OK, some tech stuff (skip if you wish):
DRAMs use multiplexed addressing. When reading or writing a DRAM chip, first a
ROW address is loaded on the DRAM address pins, and a pulse is given on a DRAM
pin called RAS. Then, the column address is given on the address pin, and a
pulse is given on another DRAM pin called CAS. The total time it takes from
the original RAS pulse until the data is out, is the DRAM access time.
Original DRAMs (10 years ago), needed a RAS/CAS pulse pair for every word
read. This made them VERY slow.
Newer Fast Page Mode DRAMs Can have a single RAS pulse and then multiple CAS
pulses (with different column addresses). This reduces the time to get the
next data word in memory (after the first word) from 70ns to 30ns.
EDO (or Extended Data Out) DRAMs has an extra 8 or 16 bit register (depending
on the DRAM width), which is cloced by the CAS lines.
On FPM DRAMs, the CAS line will tri-state the data pins when it goes high,
which takes ~10ns to turn off, and another 15ns to turn on again, which gives
you a very narrow (30-15-10=5ns) window in which you can sample the data if
you still want to keep the FPM DRAMs clicking at 30ns/word.
EDO DRAMs will never tri-state the data lines. Instead, a CAS pulse will latch
the new data on the output register, hence the data will stay on the data bus
even when CAS goes high. This means your motherboard has almost all 30ns to
sample the data. In reality it means that EDO memory can run at the 30ns
theoretical rate which FPM memory is also capable of. EDO and FPM costs
approx. the same now, because their design is almost identical, and as far as
I know, they even share most of the chip masks during the manufacturing
process (the metal layers are probably different in FPM to bypass the EDO
regisetrs).
>I didn't say EDO is supported on all Pentiums. I said it's pointless on
>486s since even if you CAN get it to work, it won't run in EDO mode...
>Same with Pentiums -- many of those that supposedly don't support EDO will
>still run EDO but as non-EDO SIMMs.
This is not guaranteed, and I wouldn't recommend it. Motherboard designs which
are not intended for EDO may try to drive two chips at the same time, which is
OK with FPM (wince you can select one of the chips into tri-state with the CAS
line), but NOT with EDO. You MAY damage your EDO SIMMs, when two or more SIMMs
fight for driving the data bus with different voltage levels.
>Awaiting to be proven wrong,
You got it. (With pleasure!).
>Ron.
udi
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