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Re[4]: Experience with 18G IDE HD



Udi Finkelstein <udif@bigfoot.com> wrote:

>  >Applying this logics to RAM would suggest that level-2 cache should be just 
>  >twice as big as level-1 and the latter shouldn't exceed the doubled total
>  >storage value of CPU registers. Actually, saying a fixed amount "is enough"
>  >means there is no sense in multi-level caches at all.
>  
>  Nope. your example falls for a basic mistake. L1, L2 are *caches* for the
>  main memory. The disk buffer calculation I did was for a disk **buffer**.
>  caches were meant to exploit the "the 80/20 rule" (AKA "Parto's rule" IIRC),
>  while buffers were simply meant to balance between different channels with
>  different peak/sustained transfer speeds. cache access pattern is pretty
>  random (you gets different bits and pieces of it hit every time), while a
>  buffer basically behaves as a FIFO.

Right, the analogy here wasn't good. Notice, however, that the memory chip(s) on
the HD controller serve _both_ as cache and buffers - depending on the sort of
task being executed. It's somewhat similar to "cached" and "buffers" in the
output of `top' or `free', in which case both are, of course, physically reside
in the same RAM, but the OS decides how to share it depending on the situation.
Granted, the logics behind this tuning for a HD is much simpler then for OS, but
I'd still assume high-profile disks (usually, == SCSI) are smarter in this
respect, too. And of course, larger caches help keeping both parts of a
resonable size. (BTW, continuing the analogy with OS, the "total" reported by
`free' is the physical amount of RAM minus what kernel uses; and in the HD
cache, the real amount of memory available for buffering/caching is the total
minus what the disk BIOS occupies. For example, IIRC, in a Quantum IDE disk
(Fireball ?) w/ 128KB cache the BIOS takes 32KB, hence leaving only 96KB for the
 real work...).

Regards,

Evgeny


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